This invention relates to analog computation, and in particular relates to circuitry for analog computation that includes charge sharing components.
Discrete time, or more generally discrete sample (e.g., spatial sample), signal processing has been implemented using analog signals. For example, a wide range of what are often referred to as “switched capacitor” filters are used, generally making us of a technique of charge transfer using active amplifier stages, whereby a signal represented by charge on capacitive elements at an input of an amplifier stage is transferred to charge on capacitive elements at an output of the amplifier stage. An advantage of circuitry that directly processes analog signals is avoiding the need to convert the signal levels to digital form and reduced circuit resources required to process the signal levels in analog form and/or higher clocking rates, as compared to use of a digital arithmetic unit of digital signal processor.
Discrete time processing of analog signals, for instance discrete time signal processing or computation of signal transforms, may require scaling of signal values according to configurable scale factors, which may be provided in digital form. One approach to implementing such scale factors makes use of multiplying digital to analog converters.
However, such an approach may have limitations based on factors such as power consumption and circuit area.
Another approach to discrete time analog signal processing makes use of active elements for combining analog signals. For example, one approach to implementing a finite impulse response filter is to use a capacitor array (e.g., a tapped delay line) to store signal values, and a set of analog multipliers with controllable gain that scale the voltages at the outputs of the array prior to combination to determine the output of the filter.